Software Development. and Programming of Multicore SOC

Transcription

1 2009 Software Development and Programming of Multicore SOC Ahmed A. Jerraya CEA-LETI 1

2 MPSoC: HW and SW Architecture MPSoC Focus of this talk: Hardware nodes for performance Software nodes for flexibility Communication network Programming and Software node: Design of MPSOC Specific CPU subsystem GPP, = DSP, ASIP,... I/O and memory architecture HW-SW Interfaces Layered SW architecture Abstraction and Application code (threads) Hardware dependent software Refinement A programming model abstracts HW-SW interfaces for SW design. Hardware Node Software Node Communication Network Operating System SW application SW interface HAL HW/SW Specific I/O CPU MEM Interfaces DMA bridge NI HW COPRO HW PROTOCOL 2

3 Computing market Trends Outline Multiprocessor System on Chip: HW and SW Architectures Programming strategies: HW-SW interfaces abstraction SW Design Strategies for MPSoC: Gradual refinement Probing further, MPSoC with NoC Conclusions 3

4 Computing in Semiconductor market 100 B$ in 100 B$ in Computing for speed performances Computing for cost and Power/speed Performances 4

5 SOC Networking Driver Trends [ITRS] 4 Cores in 2007, 10 in 2010 and 100 in

6 SOC Consumer Portable Trends [ITRS] 32 Cores in in

7 SOC Consumer Stationary Trends [ITRS] 10TF = Average Top 500 HPC in 7

8 SoC Design Cost Trends Traditional Model Trend Développment Product 2/3 Developpment Plateform Techno. 1/3 Cost X5 65 to 32nm SW Architecture HW Design Design 40% CAD/Lab IC 10% Si Fab [MEDEA+Forum] [HDTV ST] Hardware dependant SW 50% [Ghenassia ST] +16% /an Application SW HW design CAD/Lab Si Fab Developpement Product 3/4 Developpement Plateform 1/4 8

9 SoC Design technology Trends Applications SW SW HW CAD/Lab Techno Plateform Si Fab SW -Méthods -MW -OS SW HW-SW Ifce HW IC Design Variability DFM CAD/Lab Techno Plateform Si Fab Performances costs Reliability Applications 9

10 Computing market Trends SW Design Strategies for MPSoC: Outline Multiprocessor System on Chip: HW and SW Architectures Programming strategies: HW-SW interfaces abstraction Probing further, MPSoC with NoC Conclusions Gradual refinement 10

11 MPSoC HW and SW Architectures CPUa HW CPUa... SW stack a SW stack... µcontroller HW Mem HW SW stack b DSP Homogeneous architecture Multiple Instances of one CPU 1 SW stack Standard programming model DSP+µcontroller (TI OMAP) 2 X SW stacks 2 X OS Separate programming Models SW stack a CPUa... SW stack x CPUx HW IP Heterogeneous MPSoC Multiple CPU Models Multiple CPU Clusters NoC Multiple SW stacks 11

12 Application specific MPSoC Diopsis Tile [ESWEEK06] ARM9 SS MEM SS DXM SRAM ARM9 SS DSP SS Bridge Bridge ARM9 ROM MEM SS POT SS (Periph. On Tile): I/O peripherals System peripherals Timer Bridge AMBA AHB POT SS mailbox PIC Bridge DMA DSP SS mailbox PMEM Interconnect: AMBA bus AIC SPI REG DMEM DSP Local & global memories accessible by both processing units Different communication schemes between CPUs [Popovicci] 12

13 Classical SW design flow to interface HW Programming Model: Abstract HW at Different level Discontinuities: Compilation: Generally ignore the CPU environment (Interrupts, Complex I/O) Sys.lib: adapt for different HW MMAP: Adapt to different CPU-memory architecture User.lib: to make the flow efficient for the application Application Architecture Sys.lib Program + API Calls Compiler Code+Calls Linker Executable Code Programming Model (API) MMAP User.lib 13

14 My SW Stack organization Layered SW Stack Application code SW code of tasks mapped on the CPU INIT HdS (Hardware dependent SW) OS + Communication + HAL (Hardware Abstraction Layer) Different SW components need to be validated incrementally Layers corresponds to Different SW abstraction levels HW platform model at each abstraction level Tasks init. T1 Tn HDS API Communication HAL OS HAL API Software Stack 14

15 Existing SoC Software generation environments High level application model (function + mapping) T1 T2 T3 T4 Software architecture parameters Simulation, performances analysis Software Stack Tasks I T1 T4 HDS API COM OS HAL API HPPC 09 Ahmed HAL Jerraya code For each Stack software generation Tasks init. Architecture COM Specific library libraries and tools Software stack composition OS library HAL library 15

16 Architecture specific SW design Challenges Application Memory access protocols DMA, HW I/O Processor architecture OS architecture [O Nils2001] HW-SW Interfaces Design SW Code / OS micro-processor Interrupt ADR Data IO HW A B C D Hardware 16

17 Computing market Trends SW Design Strategies for MPSoC: Outline Multiprocessor System on Chip: HW and SW Architectures Programming strategies: HW-SW interfaces abstraction Probing further, MPSoC with NoC Conclusions Gradual refinement 17

18 Classical High Level Programming: Abstract HW-SW Interfaces Abstract HW model for SW design Programming language with implicit primitives (e.g. module hierarchy & threads in SystemC) API: Application Programming Interface (MPI, Posix Threads) Simulation model (MPICH, Linux) Used by SW community to free the SW designer from knowing HW details. Different programming styles (Shared mem, Mesg Passing, Streaming ) Facilitate porting of application SW over different architectures that support the same API. SW modules SW 1 SW 2 SW n SW modules API HW dependent SW (HDS) HW architecture Implementation API... SW modules API Execution Environment Simulation 18

19 Defining programming models for SoC Application SW Designer: A set of system calls used to hide the underlying execution platform. Also Called Programming Model System SW designer: Low level SW implementation of the programming Model for a given HW architecture. HW designer: A set of registers, control signals and more sophisticated adaptors to link CPU to HW subsystems. CPU is the ultimate HW-SW Interface Sequential scheme assuming HW is ready to start low level SW design Programming model for SoC Abstracts both HW and SW in addition to CPU Hides HW-SW interfaces tradeoff Sequential SW program Call HW (x, y, z) x y z HW function wait start API HW Dependant SW CPU HW-SW (local Interfaces Architecture) = data Programming Model Start done x y z 19

20 Programming models, the GAP SoC Design Programming Model RTL (Verilog, BinSW) Virtual Prototype (RTL HW, BinSW, e.g. SystemC) Explicit concepts ALL Detailed HW implementation ALL RTL HW CPU organization Mixed Abstract HW-SW Interfaces models MPI NONE Distributed SW Design RT-CORBA High Level Synchronisation Communication NONE CORBA SDL - Concurrency - Threading NONE 20

21 Classical SoC Design : The HW-SW GAPS Software Sub-System Software Thread 1 Software Thread 2 Fully implicit HW/SW Interface Hardware Software Sub-System Software Software Thread 1 Thread 1 Abstract GAP HW/SW Interface Hardware SW Binary Appli OS HAL ISS IT Ctrl Fully explicit HW/SW Interface MEM FIFO HW System Level Functional specification Partition ning Software design Hardware/Software Early HW/SW integration discontinuity Integration Virtual Prototype ISA/RTL Hardware design [Gerin ASPDAC 07] Correction cycle 21

22 Programming Models for MPSoC RTL (Verilog, BinSW) Virtual Prototype (RTL HW, BinSW, e.g. SystemC) SoC Design Programming Model Explicit concepts ALL Detailed HW implementation ALL Transaction Accurate (TLM HW, TLM SW, e.g. SystemC++) -OS - Specific I/O -CPU Subsystem - Explicit HW modules Virtual Architecture (Abstract HW, Threads, e.g. SystemC, Simulink) Communication/ Computation Modules Abstract Interconnect New HW-SW Abstraction levels Hiding CPU in addition to HW & SW Distributed SW Design MPI RT-CORBA CORBA SDL NONE RTL HW CPU organization Synchronisation Communication NONE - Concurrenc - Threading NONE 22

23 Virtual Architecture model - Explicit SW communication API - Explicit System Interconnect - Implicit HDS (OS, Communication Implementation) - Typical Models: TTL, DSoC, Pthreads HW Node SW Node SW Node VA_BFM to Abstract HDS & CPU Sub- System Model Software Thread 1 Software Thread 2 HDS API Explicit Interconnect Native SW execution on Host 23

24 SW code at Virtual Architecture level Memory declaration Computation code Communication code using HdS API Specific mapping to platform channels T1 HDS API Abstract CPU SS1 HW SS Interconnect T2 HDS API T3 HDS API Abstract CPU SS2 Task code of T1 static int B[10], C[20], D[10]; void task_t1( ) { while(1) { recv_data (reg_ch, B, 10); F1(B,C); F2(C,D); send_data (gmem_ch, D, 10); } } Memory Communication API Computation code Communication API Communication primitive void recv_data (REG_Ch* ch, void* dst, int size) { dst = ch->read (ch->address,size); } class REG_Ch : public sc_prim_channel { word *buffer; public: word * read (unsigned int addr,int size) { for (i=0; i<size; i++) *(ret+i)=*(buffer + addr +i); return ret; } }; 24

25 Transaction Accurate model HW Node SW Node - Explicit OS - Explicit CPU Subsystem Architecture - Implicit CPU/HAL (TA_BFM) - Transaction/cycle accurate HW - Typical Model : Native SW Execution [ST/TIMA/Coware/ ] Interconnect SW Node Mem I/O DMA TA_BFM to abstract CPU & Hal HW Network Accel. interface Software Thread 1 Software Thread 2 HDS API Virtual Architecture OS HAL API Specific I/O Native SW execution on Host 25

26 SW code at Transaction Accurate level HdS responsible for task and HW resources management Task code integration with OS and HdS API implementation Communication (Explicit communication protocol ) Example of TA SW code main.c extern void task_t2 (void); void start (void){ create_task(task_t2); } Abstract CPU1 Interface Communication SW void recv_data (ch,dst,size) { switch (ch.protocol){ case FIFO: If (ch.state==empty) schedule(); case REG: dst = _io_read_reg (ch.addr,size); task_t2.c OS channel ch_fifo,ch_reg; void schedule(void) { void task_t2(void ) { int old_tid=cur_tid; recv_data (ch_fifo,b, 10); cur_tid=new_tid; recv_data (ch_reg,c,20); cxt_switch(old_tid.cxt,cur_tid.cxt); } } T2 T3 HDS API Comm OS HAL API CPU-SS1 Memory Periph Main HW SS Interconnect Abstract CPU2 Interface Memory Periph 26

27 Computing market Trends Outline Multiprocessor System on Chip: HW and SW Architectures Programming strategies: HW-SW interfaces abstraction SW Design Strategies for MPSoC: Gradual refinement Probing further, MPSoC with NoC Conclusions 27

28 Ideal Design Flow ARM7 Mem Local Bus interface Periph.... XTENSA Mem Local Bus Architecture interface Periph. Application Hardware Architecture Template Global Interconnect HW Lib 1 Mapping Architecture/Alogoritm Mapping (Simulink) HW Models. SW Gen. SW Lib Simulink Model Virtual Prototype Interconnect VP Model 28

29 Automatic code generation: Gradual refinement [Popovicci07, Bouchima 06, Gauthier 03] Seamless refinement at four abstraction levels: Software Design/Debug Automatic Code Generation CPU SS2 Thread Thread Main 1 Main 2 Hardware Models App Hardware App HdS Target CPU HW-SW Codesign OS and HW codesign Design Platform Abstractions port port port port Platform Abstractions Abstract Channels Interconnect Interconnect System level model (Simulink CAAM) Virtual architecture Model (SystemC) Transaction accurate (SystemC) Virtual prototype (SystemC) 29

30 Simulink CAAM of M-JPEG Decoder Three CPUs (ARM, Xtensa) Communication Units (GFIFO, HWFIFO, SWFIFO) [RSP2007 DAC07] Architecture Layer Subsystem Layer 30

31 Experiment Results of MJPEG 10-frame QVGA (320x240) JPEG stream RTW: sequential program on the host machine CPU1 CPU2 CPU3 Simulink: Simulation in Simulink GUI 3ARM ARM7 ARM7 ARM7 VA: System C model without HW information 2XT1ARM Xtensa Xtensa ARM TA: Abstract CPU + Other devices (SC TLM) 1ARM2XT ARM Xtensa Xtensa VP: Cycle Accurate ISS + Other devices (SC TLM) 3XT Xtensa Xtensa Xtensa The architecture models at different abstraction levels provide trade-off alternatives between simulation time and architecture detail. Three ARM7 Subsystems 31

32 Performance Analysis of MJPEG percentage of total cycles ARM 2XT1ARM these performance analysis 10 results, 7, designers 2 task allocation to the 0 CPU1 processors CPU2so CPU3 CPU1 CPU2 CPU3 77 Using these can optimize task allocation that each processor has enough margins for future 1ARM2XT 3XT additional functions CPU1 CPU2 CPU3 57 percentage of total cycles CPU1 CPU2 CPU3 32

33 Computing market Trends Outline Multiprocessor System on Chip: HW and SW Architectures Programming strategies: HW-SW interfaces abstraction SW Design Strategies for MPSoC: Gradual refinement Probing further, MPSoC with NoC Conclusions 33

34 What is an MPSoC based on NoC? NoC is an interconnection structure for exchanging information on a chip between heterogeneous or homogeneous HW/SW resources CC RH CC DSP CC RH CC IP LCG LCG LCG LCG CC MEM CC CPU CC MEM CC µc LCG LCG LCG LCG CC IP CC RH CC DSP CC IP LCG LCG LCG LCG CC MEM CC DSP CC RH CC MEM LCG LCG LCG LCG 34

35 AMBRIC A chip based on 45 clusters of 8 processors 4,6 Mbits of distributed RAM The SR : a simpler 32-bit streaming RISC CPU, used for managing channel traffic The SRD : a 32-bit streaming RISC processor with DSP extensions for mathintensive processing An architecture designed to support data flow applications A complete toolkit to assist the programmer to manage 360 processors [Tom Halfhill, "Ambric's New Parallel Processor", 09 Ahmed Jerraya MicroprocessorHPPC Report, October 10, 2006] 35

36 PicoChip PC205 A chip for wireless application (WiMax, WCDMA) An array based on 248 LIW DSP cores Distributed and shared memory The need for accelerator blocks to meet real-time performance (Turbo Coder, IFFT/FFT, ) An ARM9 processor for integration of MAC functions PicoVHDL programming model [A. Duller, G. Panesar, and D. Towner, Parallel Processing - the picochip way!, Communicating Processing Architectures 2003, pp , 2003] 36

37 INTEL TeraScale A high complexity «Terascale» chip 4GHz clock frequency 1,28 TFlop of performance 65 nm CMOS Process 100 Million transistors 275 mm² die area A scalable architecture to manage complexity A 10x8 tile pattern A tile of 3mm² An in-order VLIW core mesh NoC A tile designed for GP applications with 2 FP units No specific tools for programming, Terascale Program with Berkeley [S. Vangal et al., "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS," IEEE ISSCC, Feb. 2007] 37

38 Programming = Configure Protocol Stack Programming model of the NoC-based platform is essential. It can determine : Reconfiguration management Task synchronization Power management Bandwidth allocation End-to-end flow control Protocol wrappers Packet routing GALS strategy OSI Transmission level 38

39 SW code and Configuration Parameters for HW Layers SW Code is generated for the upper layers Configuration parameters are generated for the layers implemented in HW, generally the four lower layers of the OSI reference model Physical layer: determines the number and length of wires connecting resources and switches. Unit of communication: electrical signal Data link layer: defines a protocol to transmit information between entities (switch, resource). It may include flow control and error correction. Unit : bits and words Network layer: defines how data are transmitted over the network from an sender to a receiver (routing algorithm) Unit : packet, flit Transport layer: establishes and maintains end-toend connections. Its performs packet segmentation and reassembly and ensure message ordering (Resource Network Interface). Unit : message switch switch Ressource RNI switch switch switch Ressource 39

40 Application complexity: n (wifi) scrambler Encoder parser FEC encoder FEC encoder Stream parser interleaving interleaving interleaving interleaving mapping mapping mapping mapping BPSK to 64-QAM STBC (option) CS CS CS Spatial mapping (option) IFFT IFFT IFFT IFFT CS CS CS Cyclic Shift GI Insertion + Windowing GI GI GI GI 1 to 4 Spatial Streams (SS) 1 to 4 Space-Time Streams (STS) Example of n encoding stream n 144 communications modes 2 potential coding streams, 1 to 4 antennas 1 to 4 spatial streams 1 to 4 space-time streams 40

41 Application Example Traffic (RX) RX Mem1 EPO OFDM MOD. ALAM. MOD.. CDMA MOD. MAPP. BIT INTER. RX Mem2 TURBO CODER RAM 1 CPU RAM 2 EXT RAM CTL Th. Max : 3.2 Gb/s Th. Max : 6.4 Gb/s 2.08 Gb/s ROTOR EQUAL. CHANNEL EST. CONV. DEC. ETHER NET 1.7 Gb/s 0.85 Gb/s 0.03 Gb/s FRAME SYNC. OFDM DEMOD. CDMA DEMOD. DE- MAP DE- INTER 41

42 System design for MPSoC/NoC [Leti08] SME (RAM) rotor rx_ofdmchan_est dmap SME (RAM) Platform XML model topology functions rotor rx_ofdm equal rx_fht Application Model Platform model SME (RAM) rotor rx_ofdm chan_est dmap SME (RAM) rotor rx_ofdm equal rx_fht Application Simulation Optimisation Debug SW Code and Configuration files SME (RAM) rotor rx_ofdmchan_est rotor rx_ofdm Semi-automatic Mapping End equal rx_fht dmap SME (RAM) SME rotor chan est rx ofdm equal dmap rx fht 42

43 Computing market Trends Outline Multiprocessor System on Chip: HW and SW Architectures Programming strategies: HW-SW interfaces abstraction SW Design Strategies for MPSoC: Gradual refinement Probing further, MPSoC with NoC Conclusions 43

44 Design Technologies: The Virtuous cycle New architectures require new design methods Mem SW Code / OS Interrupt micro-processor ADR Data e.g. programming z Mem DDR Analog New design methods implies new models and tools z IO HW Proc Proc Mem Mem Proc Proc Die 3 A B C Die 2 D Hardware I/O Host. Die 1 Abstract HW/SW Interface e.g. HW-SW Abstraction and Generation for MPSoC Using the new design tools and models allow the design of New Architectures z e.g. MPSoC with NoC. 44

45 Conclusions HW-SW interfaces MPSoC requires multiple SW stacks Application-specific hardware & software Programming strategies Abstract specific HW-SW architectures for a better match between HW & SW Different abstraction levels for early application SW & HDS validation Design strategies: Platform models and SW refinement at different abstraction levels Future trends: More Cores 45

46 Many thanks Marc Belleville, Didier Lattard, Jean René Lequeypes and Fabien Clermidy from LETI Prof F. Pétrot, Prof. F. Rousseau P. Gerin from TIMA K. Popovici, from Mathwork 46

47 Innovation for industry 47

48 Plan to join us on June at Minatec Crossroads For more information : 48