PIC 16F628. I.1. Caractéristiques. I.2. Brochage. Microchip PIC 16F628 M. Deloizy 1. Microchip FLASH-Based 8-bit CMOS Microcontroller

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1 Microchip PIC 16F628 M. Deloizy 1 PIC 16F628 Microchip FLASH-Based 8-bit CMOS Microcontroller I.. Présentation générale I.1. Caractéristiques CPU RISC 35 instructions (exécutées en 200ns) fonctionnement statique à 20 MHz 2 K-mots mémoire programme (FLASH) 224 octets RAM 128 octets EEPROM 15 lignes d Entrées/sorties Module comparateur analogique 3 timers (deux 8 bits et un 16 bits) module capture/comparaison/pwm USART Fonctionnement de 3.0 à 5.5V (version F) ou 2.0 à 5.5V (LF) Consommation : < 2 ma en 5V, 4MHz 15 µa en 3V, 32kHz < 1 µa en standby (3V) I.2. Brochage

2 Microchip PIC 16F628 M. Deloizy 2 I.3. Description du brochage Name DIP Pin # I/O/P Type Buffer Type Description RA0/AN0 17 I/O ST Bi-directional I/O port/analog comparator input RA1/AN1 18 I/O ST Bi-directional I/O port/analog comparator input RA2/AN2/VREF 1 I/O ST Bi-directional I/O port/analog comparator input/vref out-put RA3/AN3/CMP1 2 I/O ST RA4/T0CKI/CMP2 3 I/O ST RA5/MCLR/THV 4 I ST RA6/OSC2/CLKOUT 15 I/O ST Bi-directional I/O port/analog comparator input/comparator output Bi-directional I/O port/can be configured as T0CKI/comparator output Input port/master clear (reset input/programming voltage input. When configured as MCLR, this pin is an active low reset to the device. Voltage on MCLR/THV must not exceed VDD during normal device operation. Bi-directional I/O port/oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In ER mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. RA7/OSC1/CLKIN 16 I/O ST Bi-directional I/O port/oscillator crystal input/external clock source input. ER biasing pin. Bi-directional I/O port/external interrupt. Can be software RB0/INT 6 I/O TTL/ST (1) programmed for internal weak pull-up. Bi-directional I/O port/ USART receive pin/synchronous data RB1/RX/DT 7 I/O TTL/ST (3) I/O. Can be software programmed for internal weak pull-up. Bi-directional I/O port/ USART transmit pin/synchronous clock RB2/TX/CK 8 I/O TTL/ST (3) I/O. Can be software programmed for internal weak pull-up. Bi-directional I/O port/capture/compare/pwm I/O. Can be RB3/CCP1 9 I/O TTL/ST (4) software programmed for internal weak pull-up. Bi-directional I/O port/low voltage programming input pin. Wake-up from SLEEP on pin change. Can be software RB4/PGM 10 I/O TTL/ST (5) programmed for internal weak pull-up. When low voltage programming is enabled, the interrupt on pin change and weak pull-up resistor are disabled RB5 11 I/O TTL Bi-directional I/O port/wake-up from SLEEP on pin change. Can be software programmed for internal weak pull-up. RB6/T1OSO/T1CKI 12 I/O TTL/ST (2) input. Wake up from SLEEP on pin change. Can be software Bi-directional I/O port/timer1 oscillator output/timer1 clock programmed for internal weak pull-up. RB7/T1OSI 13 I/O TTL/ST (2) SLEEP on pin change. Can be software programmed for internal Bi-directional I/O port/timer1 oscillator input. Wake up from weak pull-up. VSS 5 P Ground reference for logic and I/O pins. VDD 14 P Positive supply for logic and I/O pins. Legend: O = output I/O = input/output P = power = Not used I = Input ST = Schmitt Trigger input TTL = TTL input I/OD =input/open drain output Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode. Note 3: This buffer is a Schmitt Trigger I/O when used in USART/Synchronous mode. Note 4: This buffer is a Schmitt Trigger I/O when used in CCP mode. Note 5: This buffer is a Schmitt Trigger input when used in low voltage program mode.

3 Microchip PIC 16F628 M. Deloizy 3 II.. Architecture interne Architecture Harvard mémoire données 8 bits mémoire programme 14 bits SFRs en mémoire de données. ALU 8 bits 1 registre de travail (W : working reg.) 8 bits flags du registre STATUS associés à ALU : C (Carry) DC (Digit Carry) Z (Zero) Pile sur 8 niveaux

4 Microchip PIC 16F628 M. Deloizy 4 II.1. Organisation mémoire II.1.a. Mémoire programme 2 k-mots de 14 bits (0000h-07FFh) cyclique 0800h 0000h PC 13 bits Vecteur Reset en 0000h Vecteur d it en 0004h II.1.b. Pile Non implantée dans les plans mémoire Accessible par instructions spécifiques CALL, RETURN, RETFIE, RETLW 8 niveaux (structure de buffer circulaire) II.1.c. Mémoire de données 4 banques de 128 octets (00h-7Fh) contient SFRs (32 premiers octets de chaque banque) Registres à usage général (RAM statique) : 020h-07Fh 0A0h-0FFh 120h-14Fh 170h-17Fh 1F0h-1FFh Mémoire commune (16 octets en ad. hautes) dans chaque banque visible en 70h-7Fh

5 Microchip PIC 16F628 M. Deloizy 5 Plan mémoire :

6 Microchip PIC 16F628 M. Deloizy 6 II.1.d. SFRs STATUS registre d état du processeur bit 7: bit 6-5: bit 4: bit 3: bit 2: bit 1: bit 0: IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

7 Microchip PIC 16F628 M. Deloizy 7 OPTION registre de configuration bit 7: bit 6: bit 5: bit 4: bit 3: bit 2-0: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate : 2 1 : : 4 1 : : 8 1 : : 16 1 : : 32 1 : : 64 1 : : : : : 128

8 Microchip PIC 16F628 M. Deloizy 8 INTCON Autorisation des interruptions bit 7: GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state

9 Microchip PIC 16F628 M. Deloizy 9 PIE1 Autorisation des interruptions bit 7: EEIE: EE Write Complete Interrupt Enable Bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt bit 6: CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 5: RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4: TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3: Unimplemented: Read as 0 bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt

10 Microchip PIC 16F628 M. Deloizy 10 PIR1 Registre d indicateurs d interruptions reçues bit 7: EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started bit 6: CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed 0 = Comparator input has not changed bit 5: RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empty bit 4: TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full bit 3: Unimplemented: Read as 0 bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0= TMR1 register did not overflow

11 Microchip PIC 16F628 M. Deloizy 11 PCON registre de configuration bit 7-4,2:Unimplemented: Read as '0' bit 3: OSCF: INTRC/ER oscillator speed 1 = 4 MHz typical (1) 0 = 37 KHz typical bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Poweron Reset occurs) bit 0: BOD: Brown-out Detect Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brownout Reset occurs) Note 1: When in ER oscillator mode, setting OSCF = 1 will cause the oscillator speed to change to the speed specified by the external resistor. PCL et PCLATH constitution de PC (13 bits)

12 Microchip PIC 16F628 M. Deloizy 12 INDF et FSR Adressage indirect FSR contient l adresse de la donnée L opération de lecture ou d écriture sur INDF porte en réalité sur la donnée pointée par FSR. Exemple : effacement de la mémoire 20h à 2Fh movlw 0x20 ;initialize pointer movwf FSR ;to RAM NEXT: clrf INDF ;clear INDF register incf FSR ;inc pointer btfss FSR,4 ;all done? goto NEXT ;no clear next ;yes continue CONTINUE:

13 Microchip PIC 16F628 M. Deloizy 13 II.2. Mémoire EEPROM Permet de sauvegarder des données (mémoire non volatile) Ecritures/lectures non «instantanées» II.2.a. EEDATA : Contient la donnée lue ou à écrire II.2.b. EEADR : Indique l adresse de la donnée bit 7 Unimplemented Address: Must be set to '0' bit 6:0 EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation II.2.c. EECON1 : Indique le type d opération à réaliser. bit 7:4 Unimplemented: Read as '0' bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR reset, any WDT reset during normal operation or BOD detect) 0 = The write operation completed bit 2 WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM bit 1 WR: Write Control bit 1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software. 0 = Write cycle to the data EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software). 0 = Does not initiate an EEPROM read

14 Microchip PIC 16F628 M. Deloizy 14 III.. Fonctionnements spéciaux III.1. Mot de configuration Accessible uniquement en phase de programmation (électrique)

15 Microchip PIC 16F628 M. Deloizy 15 III.2. Oscillateur III.2.a. Oscillateur à quartz (ou résonateurs céramiques) III.2.b. Horloge externe III.2.c. Oscillateur externe Il est préférable d utiliser un oscillateur intégré (plus stable). III.2.d. Résistance externe Pour applications ne nécessitant pas une grande précision temporelle. La résistance doit être comprise entre 38k et 1MΩ Fournit une horloge entre 10kHz et 8MHz III.2.e. RC interne Fournit en interne un oscillateur à 4MHz (5V / 25 C)

16 Microchip PIC 16F628 M. Deloizy 16 III.3. Démarrage du système 6 possibilités au démarrage du système : Power on reset (POR) mise sous tension du système MCLR activé pendant fonctionnement normal MCLR activé pendant mode SLEEP Watchdog pendant fonctionnement normal Watchdog pendant le mode SLEEP Chute de la tension d alimentation (Brown-Out Detect) quand Vcc tombe en dessous de 4V. Configurations possibles (flags de STATUS & PCON) POR BOD TO PD 0 x 1 1 Power-on-reset 1 0 x x Brown-out Detect u WDT Reset WDT Wake-up 1 1 u u MCLR reset during normal operation MCLR reset during SLEEP Legend: u = unchanged, x = unknown III.4. Interruptions Sources d interruptions : Interruption externe RB0/INT TMR0 overflow TMR1 overflow TMR2 match Changement sur PortB (RB7 :RB4) Comparateur USART CCP Masquages individuals et masquage global dans INTCON. Quand it demandée : GIE (Global Interrupt Enable) mis à 0 (interdit autres it) Adresse de retour empilée PC chargé avec 0004h sauvegarder W et STATUS (pas dans la pile!) vérification de la source d it traitement de l it acquittement de l it par remise à 0 des flags d it RETFIE termine la routine d it (et remet GIE à 1).

17 Microchip PIC 16F628 M. Deloizy 17 Sauvegarde de W et STATUS en RAM : MOVWF W_TEMP ;copy W to temp register, could be in either bank SWAPF STATUS,W ;swap status to be saved into W BCF STATUS,RP0 ;change to bank 0 regardless of current bank MOVWF ST_TEMP ;save status to bank 0 register : : (ISR) : SWAPF ST_TEMP,W ;swap ST_TEMP register into W, ;sets bank to original state MOVWF STATUS ;move W into STATUS register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W III.5. Watchdog compteur indépendant. Durée 18ms sans prédiviseur d horloge (jusqu à 2,3s avec) Activé par WDTE du mot de configuration Fonctionne même si horloge arrêtée (sur OSC1, OSC2) par SLEEP. En mode normal déclenchement d un RESET En mode SLEEP réveil du µp retour au fonctionnement normal. CLRWDT et SLEEP initialisent le watchdog III.6. Mode Power-down atteint par l instruction SLEEP arrête le driver de l oscillateur (arrêt de l horloge) Réveil par : MCLR Réinitialisation du système Watchdog Interruption sur RB0/INT ou RB change ou comparateur Poursuite du programme

18 Microchip PIC 16F628 M. Deloizy 18 III.7. Programmation électrique Programmation de type série - horloge - donnée - tension de programmation - alimentations (5V, GND) 2 possibilités : avec tension de programmation RB6 & RB7 maintenus à 0 pendant que Vpp passe de 0 à VIHH (V DD +3,5 à 13,5V) en basse tension (5V) bit LVP du mot de configuration mis à 1. Mode programmation atteint quand RB4=1 (interdit utilisation de RB4 en E/S) LVP peut être mis à 1 en mode «haute tension» (ce mode est toujours disponible).

19 Microchip PIC 16F628 M. Deloizy 19 IV.. Programmation logicielle IV.1. Ecriture de programmes IV.1.a. Instructions sur octets 'f' : registre (file register), de 0 à 7Fh 'd' : destination si d=0 résultat dans W si d=1 résultat dans 'f' Exemples : CLRW 0 W DECF CNT,1 CNT-1 CNT DECF CNT,0 CNT-1 W ENCORE DECFSZ REG,1 décrémente REG ; SKIP * si Zéro GOTO ENCORE brancher à ENCORE si REG 0 SUITE f défini = 1 SWAP RG1,f si RG1=F4h RG1=4Fh SUBWF AB,W AB-W W ; C=1 si résultat 0 W défini = 0 (*) : n'exécute pas l'instruction suivante. IV.1.b. Instructions sur bits 'b' : numéro du bit affecté par l'opération (0 à 7) 'f' : registre Exemples : BCF REG,3 met à 0 le bit 3 de REG BTFSC CNT,7 test du bit 7 de CNT ; SKIP si = 0 IV.1.c. Opérations littérales et de contrôle 'k' : constante de 8 ou 11 bits, ou valeur littérale Exemples : ADDLW 23 W+23 W ; k sur 8 bits CALL TOTO appel du sous pgm TOTO ; k sur 11 bits GOTO SUITE MOVLW 0x03 03h W CLRWDT remise à 0 du Watchdog SLEEP mise en veille (réveil par RESET, it ou WDT) RETLW 0x12 W=12h ; RETURN

20 Microchip PIC 16F628 M. Deloizy 20 Utilisation de RETLW (lecture d'une donnée en mémoire programme) : MOVLW 5 CALL TABLE.. TABLE ADDWF PC RETLW CT1 CT1 : valeur retournée si W=1 RETLW CT2 CT2 : valeur retournée si W=2 RETLW CT3 CT3 : valeur retournée si W=3..

21 Microchip PIC 16F628 M. Deloizy 21 IV.2. Jeu d instructions Mnemonic, Description Cycles 14-Bit Opcode Operands MSb LSb Status Notes Affected BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f dfff ffff C,DC,Z 1,2 ANDWF f, d AND W with f dfff ffff Z 1,2 CLRF f Clear f lfff ffff Z 2 CLRW - Clear W xxx xxxx Z COMF f, d Complement f dfff ffff Z 1,2 DECF f, d Decrement f dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) dfff ffff 1,2,3 INCF f, d Increment f dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) dfff ffff 1,2,3 IORWF f, d Inclusive OR W with f dfff ffff Z 1,2 MOVF f, d Move f dfff ffff Z 1,2 MOVWF f Move W to f lfff ffff NOP - No Operation xx RLF f, d Rotate Left f through Carry dfff ffff C 1,2 RRF f, d Rotate Right f through Carry dfff ffff C 1,2 SUBWF f, d Subtract W from f dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles in f dfff ffff 1,2 XORWF f, d Exclusive OR W with f dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clear f bb bfff ffff 1,2 BSF f, b Bit Set f bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W x kkkk kkkk C,DC,Z ANDLW k AND literal with W kkkk kkkk Z CALL k Call subroutine kkk kkkk kkkk CLRWDT - Clear Watchdog Timer TO,PD GOTO k Go to address kkk kkkk kkkk IORLW k Inclusive OR literal with W kkkk kkkk Z MOVLW k Move literal to W xx kkkk kkkk RETFIE - Return from interrupt RETLW k Return with literal in W xx kkkk kkkk RETURN - Return from Subroutine SLEEP - Go into standby mode TO,PD SUBLW k Subtract W from literal x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal with W kkkk kkkk Z

22 Microchip PIC 16F628 M. Deloizy 22 V.. Périphériques V.1. Ports d'entrées-sorties 2 ports 8 bits : PORTA et PORTB direction contrôlée par TRISA et TRISB V.1.a. PORTA Particularités : entrées avec trigger de Schmitt RA4 sortie drain ouvert RA5 entrée seulement autres sorties avec drivers push-pull bits de TRISA : '1' : drivers de sortie en haute impédance '0' : drivers en basse impédance PORTA multiplexé avec : - comparateurs/références de tension (CMCON & VRCON) - oscillateur. - MCLR, VPP Exemple d'initialisation CLRF PORTA ;Initialize PORTA by ;setting output data latches MOVLW 0x07 ;Turn comparators off and MOVWF CMCON ;enable pins for I/O functions BCF STATUS,RP1 BSF STATUS,RP0 ;Select Bank1 MOVLW 0x1F ;Value used to initialize ;data direction MOVWF TRISA ;Set RA<4:0> as inputs ;TRISA<5> always read as 1. ;TRISA<7:6> depend on oscillator mode

23 Microchip PIC 16F628 M. Deloizy 23 V.1.b. PORTB 8 bits bidirectionnel Possibilité tirage haut interne (OPTION.7) ( 200µA) bits de TRISB : '1' : drivers de sortie en haute impédance '0' : drivers en basse impédance PORTB multiplexé avec : - interruption externe, USART, CCP, TIMER1 in/out Possibilité de déclencher it sur changement d'état sur RB.7 à RB.4 V.2. USART (UNIVERSAL SYNCHRONOUS/ASYNCHRONOUS RECEIVER/TRANSMITTER) Communication série synchrone ou asynchrone sur pattes RB2/TX/CK and RB1/RX/DT contrôlé par : - TXSTA : état et contrôle de la transmission - RCSTA : état et contrôle de la réception - SPBRG : générateur de bauds module d'émission : module de réception :

24 Microchip PIC 16F628 M. Deloizy 24 V.2.a. TXSTA: TRANSMIT STATUS AND CONTROL REGISTER bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CSRC: Clock Source Select bit Asynchronous mode : Don t care Synchronous mode : 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as '0' BRGH: High Baud Rate Select bit Asynchronous mode : 1 = High speed 0 = Low speed Synchronous mode : Unused in this mode TRMT: Transmit Shift Register STATUS bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of transmit data. Can be PARITY bit. Note 1: SREN/CREN overrides TXEN in SYNC mode.

25 Microchip PIC 16F628 M. Deloizy 25 V.2.b. RCSTA: RECEIVE STATUS AND CONTROL REGISTER bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SPEN: Serial Port Enable bit (Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:17> are set) 1 = Serial port enabled 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don t care Synchronous mode : - master: (This bit is cleared after reception is complete) 1 = Enables single receive 0 = Disables single receive - slave: Unused in this mode CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received, and ninth bit can be used as PARITY bit Asynchronous mode 8-bit (RX9=0) : Unused in this mode Synchronous mode : Unused in this mode FERR: Framing Error bit 1 = Framing error (Can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (Can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of received data (Can be PARITY bit)

26 Microchip PIC 16F628 M. Deloizy 26 V.2.c. Générateur de Bauds contrôlé par : - SPBRG (registre 8 bits) (valeurs 0 à 255) - BRGH (TXSTA.2) Mode synchrone : Fosc Baud = avec BRGH = 0 4 SPBRG +1 Mode asynchrone : ( ) Fosc Baud = (BRGH = 0) 64 ( SPBRG +1) Fosc Baud = (BRGH = 1) 16 SPBRG +1 ( ) pour réduire l'erreur, il est préférable de prendre BRGH = 1 Exemple : si Fosc = 4MHz BRGH Baud min Baud max On veut 9600 bauds : BRGH SPBRG calculé SPBRG arrondi BAUDS obtenus Erreur 0 5, ,6 7 % 1 25, ,4 0,1 %

27 Microchip PIC 16F628 M. Deloizy 27 VI.. Annexes VI.1. Notes d'applications Description Documentation PIC16C5x/PIC16Cxx Utility Math Routines AN526 Source Code 51097a Using PWM to Generate Analog Output AN538 Software Implementation of I²C Bus Master AN554 Source Code Implementing a Table Read AN556 Using the Port B Interrupt on Change as an External AN566 Interrupt Macros for Page and Bank Switching AN586 Source Code Interfacing PICmicros to an LCD Module AN587 Source Code Adaptive Differential Pulse Code Modulation using the AN643 Source Code PIC16/17 PWM, A Software Solution using the 16CXXX Devices AN654 PIC18CXXX/PIC16CXXX DC Servomotor AN696 Source Code IEEE 754 Compliant Floating Point Routines AN575 Source Code Techniques to Disable Global Interrupts AN576 PIC16/17 Oscillator Design Guide AN588 Low Power Design Using PIC16/17 AN606 Using Timer 1 in Asynchronous Clock Mode AN580 Low-Power Real Time Clock AN582 Source Code A Real-Time Operating System for PIC16/17 AN585 Source Code Using the CCP Modules AN594 Source Code Improving the Susceptibility of an Application to ESD AN595 Implementing Ultrasonic Ranging AN597 Source Code Power-up Trouble Shooting AN607 Source Code Fixed Point Routines AN617 Source Code D/A Conversion Using PWM and R-2R Ladders to AN655 Source Code Generate Sine and DTMF Waveforms In-Circuit Serial Programming of Calibration Parameters AN656 Source Code Using a PICmicro Microcontroller Floating Point Routines AN660 Source Code CRC Generating and Checking AN730 Source Code Automatic Calibration of the WDT Time-out Period 91003a TechBrief: Using SRAM with a PIC16CXX 91011a How to Implement ICSP Using PIC16CXXX OTP 91013b MCUs Using a PIC16F877 To Develop Code for PIC16CXXX 91033a Devices TechBrief Tranformerless Power Supply 91008b BASIC PIC16/17 OSCILLATOR DESIGN GUIDE fact001 Low Frequency Magnetic Transmitter Design AN232

28 Microchip PIC 16F628 M. Deloizy 28 VI.2. Fichier template Program Files\MPLAB IDE\MCHIP_Tools\TEMPLATE\Code\f628temp.asm list p=16f628 ; list directive to define processor #include <p16f628.inc> ; processor specific variable definitions CONFIG _CP_OFF & _WDT_ON & _BODEN_ON & _PWRTE_ON & _ER_OSC_CLKOUT & _MCLRE_ON & _LVP_ON ; ' CONFIG' directive is used to embed configuration data within.asm file. ; The lables following the directive are located in the respective.inc file. ; See respective data sheet for additional information on configuration word. ;***** VARIABLE DEFINITIONS w_temp EQU 0x70 ; variable used for context saving status_temp EQU 0x71 ; variable used for context saving ;********************************************************************** ORG 0x000 ; processor reset vector goto main ; go to beginning of program ORG 0x004 ; interrupt vector location movwf w_temp ; save off current W register contents movf STATUS,w ; move status register into W register movwf status_temp ; save off contents of STATUS register ; isr code can go here or be located as a call subroutine elsewhere movf status_temp,w ; retrieve copy of STATUS register movwf STATUS ; restore pre-isr STATUS register contents swapf w_temp,f swapf w_temp,w ; restore pre-isr W register contents retfie ; return from interrupt main ; remaining code goes here END ; directive 'end of program'

29 Microchip PIC 16F628 M. Deloizy 29 Table des matières II.. Présentation générale... 1 I.1. Caractéristiques... 1 I.2. Brochage... 1 I.3. Description du brochage...2 IIII.. Architecture interne...3 II.1. Organisation mémoire...4 II.1.a. Mémoire programme...4 II.1.b. Pile...4 II.1.c. Mémoire de données...4 II.1.d. SFRs...6 II.2. Mémoire EEPROM...13 II.2.a. EEDATA :...13 II.2.b. EEADR :...13 II.2.c. EECON1 :...13 IIIIII.. Fonctionnements spéciaux...14 III.1. Mot de configuration...14 III.2. Oscillateur...15 III.2.a. Oscillateur à quartz (ou résonateurs céramiques)...15 III.2.b. Horloge externe...15 III.2.c. Oscillateur externe...15 III.2.d. Résistance externe...15 III.2.e. RC interne...15 III.3. Démarrage du système...16 III.4. Interruptions...16 III.5. Watchdog...17 III.6. Mode Power-down...17 III.7. Programmation électrique...18 IIV.. Programmation logicielle...19 IV.1. Ecriture de programmes...19 IV.1.a. Instructions sur octets...19 IV.1.b. Instructions sur bits...19 IV.1.c. Opérations littérales et de contrôle...19 IV.2. Jeu d instructions...21 V.. Périphériques V.1. Ports d'entrées-sorties V.1.a. PORTA V.1.b. PORTB V.2. USART V.2.a. TXSTA: TRANSMIT STATUS AND CONTROL REGISTER V.2.b. RCSTA: RECEIVE STATUS AND CONTROL REGISTER V.2.c. Générateur de Bauds VII.. Annexes... 27

30 Microchip PIC 16F628 M. Deloizy 30 VI.1. Notes d'applications VI.2. Fichier template... 28