Statut sur les dernières évolutions des mémoires FLASH

Transcription

1 Statut sur les dernières évolutions des mémoires FLASH Luca Perniola 1

2 Outline Definitions Economical aspects of FLASH memories How does it work? Scaling limits Main solutions envisaged Conclusion 2

3 Outline Definitions Economical aspects of FLASH memories How does it work? Scaling limits Main solutions envisaged Conclusion 3

4 Definition (1/3) What is a Non-Volatile Memory? Volatile memories Content lost when power off Non-Volatile memories Content kept when power off 4

5 Definition (2/3) History 5

6 Definition (3/3) Storage media that keeps the information without power (no refresh needed) Some Examples: Cell phones MP3 players USB keys Digital photos and so on 6

7 Outline Definitions Economical aspects of FLASH memories How does it work? Scaling limits Main solutions envisaged Conclusion 7

8 Economical aspects (1/2) 8

9 Economical aspects (2/2) 9

10 Outline Definitions Economical aspects of FLASH memories How does it work? Scaling limits Main solutions envisaged Conclusion 10

11 FLASH memory: how does it work? V G Memory Effect V G Interpoly Oxide (IPD) V S V D electrons V S V D Metal Metal Source Oxide Channel Drain Source Oxide Channel State «0» State «1» Drain Tunnel oxide The two states are defined by the presence/absence of electrons in the floating gate of the device 11

12 How to distinguish the 2 states? I D V G V G Metal V D >0 ΔV T =Q/Ctop Metal V D >0 Source Oxide Channel Drain Source Oxide Channel Drain V T0 V T1 V G Charge in the floating gate induces a shift of V T 12

13 Floating gate FLASH operation: write/erase Fowler-Nordheim (ie uniform) stress V G ~20V Metal Tunnel Oxide Oxide 1 Channel 2 Source Channel Drain V G ~-15V Oxide Floating gate 1 Floating gate Metal Tunnel Oxide 2 Floating gate Source Channel Drain Channel 13

14 FLASH operation: write/erase Hot-carrier stress V G ~ 10V 1 Floating gate Metal V D ~ 5V Channel Oxide 2 Oxide Source Channel Drain V G ~ -5V Oxide Floating gate Floating gate Metal V D ~ 5V Floating gate Source Oxide Channel Drain Channel 14

15 FLASH main architectures: NAND / NOR NOR NAND S G D G S D -Random/Fast access time -Large cell area -Mainly used for code storage -Serial/slow access time -Small cell area -Mainly used for data storage 15

16 Embedded or stand-alone NVM? Stand-alone maximum information density Leading edge tech for minimum cell dimension Complex manufacturing cost Embedded compatibility with CMOS process Maximum efficiency (low access time) Larger cell areas (thus not high storage density) Cheaper technology 16

17 Outline Definitions Economical aspects of FLASH memories How does it work? Scaling limits Main solutions envisaged Conclusion 17

18 Great challenge: how to store more information 18

19 ITRS for NOR and NAND Flash memories Year Technology Node (nm) Cell size (λ²) Cell size (µm²) Generation at prod. SLC MLC Coupling ratio Tunnel oxide EOT (nm) Interpoly oxide EOT (nm) NOR L g -stack (physical µm) Highest W/E Voltages (V) Endurance (# cycles) Retention (years) NOR Iread (ua) Max. # bits/cell 2006 NOR NAND G 8G / NOR NAN D / NOR NAND / G 16G 16G 32G E NOR NAND G 64G / E6 1E Solutions exist Solutions known Solutions NOT known CG FG Oxide CG Source Channel Drain Source FG Oxide Channel Drain 19

20 Outline Definitions Economical aspects of FLASH memories How does it work? Scaling limits Main solutions envisaged Conclusion 20

21 Main solutions Standard Bulk CMOS FG Flash 1. Development of new technologies: FeRAM MRAM OUM-PCM FPRAM Seek and Scan Molecular memories 2. Pushing the scaling limits of current technologies 2.A New Materials materials Tunnel Oxide: Crested Barriers Floating Gate: CVD discretetrap, High-ks IPD: High-k / Metal Gate 2.B New architectures Ultra-thin body SOI FET Multiple gate FETs 3D stacked arrays LETI - D2NT Research Topics: National Projects, IST Projects, MEDEA Projects, Industrial Partnerships LETI Other Departments 21

22 New materials: Re-engineering the gate stack Re-engineering the FG ONO Poly-Si SiO 2 x High-K SiO 2 x Nitride (NROM TM ) or Si-dots (nanocrystal NC ) Standard Flash Discrete-trap: Tunnel oxide ~5nm without compromising retention (robust against oxide defects). Lower operating voltages. Suppression of cells with abnormally short retention. Robustness to parasitic FG cross-talk. Multibit feasibility High-K top layer: Enhance the coupling (enhance write/erase perf) Low leakage current 22

23 Si-NC integration ATMEL/Leti Si-NCs integrated in a 32 MB NOR Flash memory product based on a 130 nm ATMEL embedded Flash technology platform NOR Si-NC 32Mb 6nm 9nm 11nm 13nm Periphery devices first to avoid Si-NC oxidation Control gate STI W 50 nm STI 23

24 Inclusion of high-k in top dielectric (1/2) SiO 2 Interpoly High-k Interpoly J in J out J in J out channel J out J in J in Floating G J out Gate Same E in tunnel and IPD J tun ~J IPD Q FG ~0 E IPD high-k <E tunnel J tun >>J IPD Q FG 0 24

25 Silicon Nanocrystals with high-k for sub 45nm (LETI at IEDM ) (2/2) 3-layers IPD Poly-Si HTO High-k HTO SiO 2 4nm 8nm 4nm 4nm 2-layers IPD Poly-Si TiN High-k HTO SiO 2 8nm 4nm 4nm (b) SiO 2 HTO HTO HfAlO Poly-Si IPD High-k HfO 2, HfAlO, or Al 2 O 3 Si-ncs O/high-k/O (3-layer) or O/high-k (2-layer) stack With or wo SiN capping (Si-nc or Si-nc/SiN memories) Threshold voltage V th [V] Si-ncs Si 6 5 O/HfO 2 /O O/HfAlO/O O/Al 2 O 3 /O O/Si 3 N 4 /O V P : 14V 17V 4 3 ~4V ~3.2V ~3V V E : -12V -15V Pulse duration [s] 25

26 New architectures: FinFLASH structure (LETI at IEDM ) 1E-3 V =1V DS (a) 4 V Erased T E =0.1s, V G =-12V G =7V (b) 1E-5 3 V G =8V Fresh V G =9V V D =2V 1E-7 2 V G =10V Written 1E-9 Erased V D =2.5V 1 V G =7,8,9,10V 1E-11 T W =100µs 0 1E E-7 1E-6 1E-5 1E-4 Gate Gate Voltage Voltage V G [V] V G [V] Write Time Write T W Time [s] T W [s] Drain Current I D [A] Threshold Voltage V TH [V] (c) V G =-12V V G =-13V V G =-14V V G =-15V E-7 1E-6 1E-5 1E-4 1E-3 0,01 0,1 Erase Time T E [s] Threshold Voltage V TH [V] Threshold Voltage V TH [V] (d) V D =2.5V V G =7V V G =8V V G =9V V -1 G =10V 1E-7 1E-6 1E-5 1E-4 Toute Write reproduction Time totale ou Tpartielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l autorisation écrite préalable du CEA All rights reserved. Any reproduction W [s] in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA 26

27 New materials & architectures: TANOS solution from SAMSUNG 30 nm generation Multi-level NAND flash for 64Gb (VLSI ) 27

28 New functionality: more information on the same bit (1/3) From 1 bit/cell to 2 bits/cell Ex: Intel StrataFLASH Ex: Saifun NROM 28

29 Multilevel FLASH (2/3) 1 bit 2 bit -Almost double the density in the same chip area -Higher control on Vth distribution (thus larger overhead, ECC ) -Slower than simple 1bit/cell 29

30 Multibit FLASH (3/3) NROM is not a floating gate device: nitride charge trap device (Quad-bit presented at IEDM 2005) 30

31 Solution: 3D stacked architectures (1/2) SAMSUNG stacked NAND concept (IEDM 2006) -Monocrystalline upper layers for better electrical properties 31

32 3D stacked architectures (2/2) TOSHIBA: Bit-cost scalable FLASH memory (VLSI & IEDM ) -Vertical bitline -better cost-effective solution (believing in TOSHIBA) -polycristalline channels, thus worse performances 32

33 Alternative approaches -Alternative technologies (not based on charge storage) aim to the "universal memory -Not easy for alternative NVMs to compete with Flash, but adequation of cost and application requirements will drive adoptions 33

34 Outline Definitions Economical aspects of FLASH memories How does it work? Scaling limits Main solutions envisaged Conclusion 34

35 Conclusion FLASH has been a consolidated mature technology for many years FLASH cell scaling has been demonstrated from 1 µm to 50 nm at production level Recent development data indicate the 45 nm node is feasible without major cell architecture innovations FLASH will remain the dominant nonvolatile memory technology, at least down to the 2X node (2016), in spite of the scaling difficulties to be addressed 35

36 Thanks for yourattention 36

37 NOR/NAND market share 37

38 Scaling Limits Gate stack scaling limits: t 1 =8-9 nm (SILC) and t 1 =6-7 nm (direct tunneling). t 2 trade-off between good coupling factor α G (t 2 ) and large ΔV th and good retention (t 2 ). t 2 t 1 CG CG FG X X L/W scaling limits: L reduction presents Short Channel Effects (SCE) or even Punchthrough. Integration of larger and larger number of cells provokes parasitic coupling between nearby cells. D D D Bulk Bulk SS 38