MAGILLEM: environnement de contrôle de flot pour la conception ESL (Electronic System Level)

Transcription

1 MAGILLEM: environnement de contrôle de flot pour la conception ESL (Electronic System Level) Atelier «outils pour l IDM» Mardi 27 janvier 2009 ENSEEIHT - Toulouse

2 Moving from traditional flow to ESL (Electronic System Level) Need for Extending traditional flow to ESL (TLM) Specifications Need for Enforcing automation of Existing flow Need for Enabling advanced features at ESL

3 IP-XACT at a glance

4 The SPIRIT Consortium

5 The SPIRIT Consortium

6 IP-XACT and tools in a design flow 1/IP Packager 2/Platform Assembly 3/Generator Studio Component IP IP-XACT Compliant Design Environment IP-XACT Compliant Generators Component XML DESIGN CAPTURE Invocation GENERATOR Chains Design XML Design XML Abstractor IP Abstractor XML IP-XACT IP Import/Export IP-XACT Compliant Objects Description 4/Flow Control Bus Definitions DESIGN BUILD Abstraction Definitions SPIRIT API TGI GENERATORS XML Configured IP Point tools Configured Output

7 IP-XACT Generators

8 Magillem Offering : Tools and Services for Design Flow Control : A 4-step ESL methodology 4.Advanced User Features 3.Flow Control Standard tools management, customization 2.System Description Assembly, Configuration, Verification 1.IP Description Data Base Builder/Migration (Metamodel)

9 Bridging the gap between Hw and Sw Align the software development tools with a common system description HW platform described in IP-XACT 1.4 (TLM and RTL) Information about the system are not duplicated and consistent Exploitation of system attributes description in order to automate code generation Register descriptions Memory map Allowing a better configurability of tools and their interoperability Interfacing tools with IP-XACT environment thanks to TGI

10 Example #1: SW driven IP Integration verification Automate VSW generation from IP-XACT Packaging each IP with CC view IP-XACT design to CSV with TGI generator Automation of the CC generation and build step HDL and RDL files Boot files IP-XACT Components IP VSW files in C Compilation Generator IP-XACT Design XML2CSV TGI Generator Connection Table (system connectivity data) Excel CSV Converter VChipGen Chip context Simulation/ Verification/ Debug HDL Netlister HDL Netlist HDL Platform Elaboration

11 Example #2: IP-XACT based debug environment config Experiments (Done in the frame of SPRINT FP6 IST project) ST MPRV (Memory Map Resources Viewer) available as a plug-in in Eclipse debugger Purpose Providing an enhanced view of the registers of peripheral IPs that are visible from the processor addressing space Automate MMRV configuration from IP-XACT Exploit the Memory map and registers description in Design and Component XML files TGI generator have access to the IP-XACT database and generates the configuration file IP-XACT Components IP-XACT Design With Memory Mapped Resources TGI Generator Configuration of the register viewer MMRV Memory Map Register Viewer Eclipse C++ Debugger

12 Merci de votre attention Demonstrations et white papers disponibles aujourd hui