Compact S-Band Amplifier in plastic package

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Claudine Chénier
il y a 5 ans
Total affichages :

1 Compact S-Band Amplifier in plastic package Z.OUARCH - UMS M.OLIVIER THALES LAS FRANCE

2 OUTLINE UMS technology portfolio Context HPA Design Package solution validation Simulations results Measurements Conclusion 2

3 UMS technology portfolio 3

4 GH25-10 technology Characteristics Lg = 0.25µm 4 SiC substrate AlGaN/GaN epitaxy T-shape gate Source connected field plate SiN passivation Air bridges between source connections EPPL listed Electrical parameters Min. Max. GH25-10 IDS+ [ma/mm] Gmmax [ms/mm] Vg100 [V] Idl 10V IdlHV 50V Power density 30V Commercial production Ramp-up Space production

5 UMS GaAs Technology / ULRC-20 / Process description ULRC technology on 4 inch wafer, 100µm thickness High MIM Capacitor Breakdown voltage : >150V BCB protection option 5

6 Context Challenges & goals Bests electrical performances High integration density Reliable solution Cost optimization (HPA topology solution & low cost package) Plastic package solutions Already used for GaN products 6

7 Context - Architecture analysis Amplifier architecture VS cost Quasi-MMIC solution Integration close to MMIC Cost close to Hybrid For Integration density & cost : Quasi-MMIC is the best solution 7

8 HPA Design - Topology New development Process & technologies: UMS Topology: Quasi-MMIC - One active die: GaN Power bar - Two passive dies: GaAs MMICs Plastic package: DFN 8X8mm² 8

glue Leadframe Low Void soldering Reference PCB Assembly steps Leadframe Die

9 Packaging / Base Line Base line: Thermal QFN/DFN Thermal drain Hot Spot Heat Die coat Die attach Leadframe Soldering PCB Die coat: protection Sintered glue Leadframe Low Void soldering Reference PCB Assembly steps Leadframe Die attach Wire bonding Die coat Molding Best trade off: Performance/Thermal/cost 9

matching : GaAs ULRC-20 with BCB (Dies B & C ) Thermally enhanced Die

10 Packaging Plateform HPA : S band in DFN 8x8mm² Leadframe: Finition NiPdAu Multi Chips - Power bar: GaN GH25 (Die A) - Input & Output matching : GaAs ULRC-20 with BCB (Dies B & C ) Thermally enhanced Die attach Au bounding wires Die coat on GaN (Die A) HPA: DFN 8x8mm² Die B Die C Die A 10

Packaging Plateform validation Die attach

Cycling Material and thickness Transition

chip PC & TC From chip to Pin Dimensions

11 Packaging Plateform validation Die attach Wire Bonding Die coat Thermal Characterization Thermal simulation Validation tests Preconditioning Thermal Cycling Material and thickness Transition definition Validation tests From chip to chip PC & TC From chip to Pin Dimensions and tolerances Validation tests (die shear, ball shear, etc) 3D EM model 11

Thermal analysis: Rth & peak junction temperature/tj_p 1.

Hot plate supply Hot plate set point Oscilloscope (Vg,Vd, Id) Vg pulse

Id C3 Current probe Thermocouple + loop sensorc2 C1 3.

Hot plate Efuse DUT Peak junction Temperature is determined using 3 methods

12 Thermal analysis: Rth & peak junction temperature/tj_p 1.Thermal Simulation at UMS (Tj_p) Tj_p: Peak junction Temperature ( UMS ref for reliability «hot spot» 2. Electrothermal Characterization at UMS (Tj_av: Average junction Temperature) Hot plate supply Hot plate set point Oscilloscope (Vg,Vd, Id) Vg pulse modulator Vd Hot plate temperature DC voltmeter : mean Vd DC voltmeter : mean Id C3 Current probe Thermocouple + loop sensorc2 C1 3.Infra scope measure at TRT (Tj_IR: Surface Temperature on specific spot size) Hot plate Efuse DUT Peak junction Temperature is determined using 3 methods Tj_p extracted from Tj_av is almost identical to Tj_p obtained by thermal simulation Hot spot measured on 4th transistor Tj_p is lower then specified value at Tc=95 C (<200 C) 12

13 HPA Design procedure / RF performance optimization Optimization on PAE and Harmonics rejection Main challenge : definition of optimum load to reach Pout_min & Pdiss_max 13

14 HPA simulation results Power Added Efficiency Vds=28V; Vgs=-3.85V (Idq=0A) Pin=39dBm Pin=38dBm Pin=37dBm Fmin Fmax For Pin = 38dBm : PAE > 50% 14

15 HPA simulation results Harmonic rejection Vds=28V; Vgs=-3.85V (Idq=0A) H2 H3 H4 Pin=37dBm Pin=38dBm Pin=39dBm Harmonic rejection H2,H3 & H4 > 40dBc 15

16 HPA measurements RF Performances Vds=28V Pin=39dBm Load 50Ohm T case = 25 C T case = 95 C Fmin Fmax Fmin Fmax PAE max = 58% at T case = 25 C PAE max = 55% at T case = 95 C 16

17 HPA measurements RF Performances T case ϵ [25 C;95 C] - Load 50Ohm Vds=28V Pin=39dBm Harmonic Rejection H2, H3 et H4 > 45dB 17

18 Conclusion Production Test validation Design to Cost Integration: Q-MMIC 3D Simulation Thermal performance Package validation (plastic package solution) HPA DFN 8x8mm² Performances at the state of the art 18

19 Thanks DGA and III-V lab for its support in the development of new technology platform 19

20 Thank you for your attention

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