EU CATRENE / ENIAC EDA Roadmap Working Group DESIGN METHODS & TOOLS Under Leadership of Livio Baldi, Numonyx

Transcription

1 2010 EU CATRENE / ENIAC EDA Roadmap Working Group DESIGN METHODS & TOOLS Under Leadership of Livio Baldi, Numonyx Ahmed A. Jerraya CEA-LETI Ahmed.jerraya@cea.fr 1

2 Working Group DESIGN METHODS & TOOLS STMicroelectronics P.G.Rolandi Infineon R.Pferdmenges NXP Peter Zegers Bosch P. Van Staa PoliTorino E. Macii CEA-LETI A. Jerraya IMEP-LAHC Ph. Ferrari Fzi-U.Tubingen W. Rosenstiel IMEC C. Martens Rudy Lauwereins IUNET E. Sangiorgi UCL D. Flandre, D. Bol David Bol Numonyx L.Baldi 2

3 Impact Factors Design is the bridge between technology and applications Impact on key applications: Design competence is the main differentiating factor for high tech industry Design efficiency is a key element in containing development costs of new products and supporting key European high tech sectors (automotive, telecom) Smart design is the key to energy saving in electronic systems. Opportunities: IP design and design services are a thriving market for SME s in Europe (more than 300 now) More than 15,000 designers in Europe Low entry barrier for SME s in design and tools. 3

4 Market Size Impact on European industry is mainly through competitiveness of semiconductor design. European systems/products e.g. automotive, automation, aviation/aerospace) need innovative electronic solutions for differentiation. Total investment in semiconductor design in Europe in is around 2.5 B. Roughly designers active in Europe. Investment on Design Tools by European semiconductor industry (IDM and fabless) was roughly 1 B$ in (25% of R&D investment) Western Europe represents 20% of the market. PCB/MCM 13% Physical 21% VHDL 42% European EDA market 2007 Total value: B$ IP & tools 15% Services 9% 4

5 Driving Forces Applications are becoming more complex in terms: Number of devices Number of implemented functions Time to mass market is reducing. Design Technologies are the key enabling factor to meet the challenge. Design Cost Time to Market 5

6 Differentiated European Market 50 Market size [%] Europe World 0 Computer & Office Automotive Consumer Government Communications Industrial 6

7 A new scenario Complexity System on Chip Covered by big EDA vendors System in Package 3D-SoC NEW Standard Logic Analog RF Power Sensors Bios Technology Heterogeneity 7

8 Planning European Research ENIAC SRA Common pan-european Strategic Research Agenda Through FP7 Workprogramme preparation Direct control through industrial committee Definition of CATRENE White Book Through national platforms FP7 Upstream R&D Joint Technology Initiative Industry + Countries + EC EUREKA CATRENE MEDEA+ Transnational programs National National programs National programs programs 8

9 CATRENE White Book ANNEX 1: Design automation sub-work areas 1. Specification and validation 2. System architecture exploration 3. Hardware-dependent software 4. Mixed analog/digital and RF 5. Electronic design automation for MEMS 6. Verification, validation and test 7. Low-power design solutions 8. Rapid system prototyping 9. Test development for SoC and SiP 10. Design for manufacturability 11. Reliability by design 12. Design methodologies/tools for fail-safe SoCs comparable to self-adapting chips 9

10 Grand Challenges in MASP Design efficiency for functional complexity Tools for Architecture Exploration and Optimization of Heterogeneous Systems Behavioral models for high level design of heterogeneous functions. Design environment for New Heterogeneous and Homogeneous Architectures and 3-D integration Hardware-software partitioning and verification. Tools for mixed analogue/digital/rf linked to system simulation, including SiP integration Tools for package-ic co-design, multi-chip and 3-D integration, PCB-interfaces, Design environment for constraint driven design for specific applications. Deterministic verification methodologies/tools Reliability and yield by design Electromagnetic Compatibility and Signal integrity Modeling of reliability effects (aging, soft errors, electro-migration, Electrostatic Damage, Electromagnetic coupling, temperature and hot spots, substrate noise) Robust system design, including reconfigurability, redundancy and ECC Yield optimization through statistical design, layout processing, yield-learning DFT Advanced DFT, especially for analogue/mixed signal and System Level BIST Verification driven design Energy efficient design Energy modelling and estimation at different abstraction levels for heterogeneous technologies Dynamic and static energy management for heterogeneous systems Thermal and variation-aware design under tight energy constraints 10

11 A Common Strategy Joint document: Vision, Mission and Strategy Differentiated Calls 11

12 A strategic vision Design Technologies are a critical enabling factor for all applications. The European trend towards More than Moore and System in Package integration requires the development of specific Design Technologies not supported by major EDA vendors. New tools will require a broad European effort with a strong participation of research centers and mediumlong term horizon. Specific methodologies require a stronger involvement of companies on specific application projects. 12

13 Innovation for industry 13